A power supply voltage detection circuit mounted on a semiconductor device generates a reset signal to reset an internal circuit of the semiconductor device during when a power supply voltage is lower than a predetermined voltage. With the use of the reset signal, malfunction of the internal circuit may be reduced while the power supply voltage is low. The power supply voltage detection circuit securely generates the reset signal also when the power supply voltage temporarily decreases and then increases again. A related art is discussed in Japanese Laid-open Patent Publication No. 2007-306351.